1. Field of the Invention
The present invention relates in general to a driving circuit. In particular, the present invention relates to a driving circuit operated in voltage switching mode to output high frequency signals.
2. Description of the Related Art
FIG. 1 shows a conventional driving circuit. The source of the PMOS transistor P10 is connected to the current source 10, the drain of the PMOS transistor P10 is connected to the NMOS transistor N10 and the source of the NMOS transistor N10 is connected to the current source 12. The gates of the PMOS transistor P10 and the NMOS transistor N10 are connected to the inverse input terminal DN. In addition, the source of the PMOS transistor P12 is connected to the current source 10, the drain of the PMOS transistor P10 is connected to the NMOS transistor N12 and the source of the NMOS transistor N12 is connected to the current source 12. The gates of the PMOS transistor P12 and the NMOS transistor N12 are connected to the input terminal D. The output resistor 14 includes terminals Q and QN, connected to the connection point of the drains of the PMOS transistor P10 and the NMOS transistor N10 and the connection point of the drains of the PMOS transistor P12 and the NMOS transistor N12, respectively. The voltage of the terminals Q and QN are both input to the first input terminal of the comparator 16 through resistors 15A and 15B having the same resistance, respectively. Thus, the voltage level of the first input terminal is half of the addition of the voltage of the terminals Q and QN. The comparator 16 compares the voltage at the first input terminal and a reference voltage VREF at the second input terminal and controls the current source 12 to make the half of the addition of the voltage of the terminals Q and QN equal to the reference voltage VREF. Thus, the voltages at the terminals Q and QN are fixed.
The conventional driving circuit shown in FIG. 1 is operated in current switch mode with common mode feedback. Here, the voltage level of the terminals DN and D are inverted. That is, when the terminal D receives a high level signal, the terminal DN receives a low level signal at the same time. Thus, the PMOS transistor P10 and the NMOS transistor N12 are turned on and the PMOS transistor P12 and the NMOS transistor N10 are turned off. Therefore, current flows through the resistor 14 from the terminal Q to the terminal QN, and constant voltage difference between the terminals Q and QN is generated and the voltage level at the terminals Q and QN is controlled by the comparator 16, wherein the comparator 16 is an operational amplifier. Conversely, when the terminal D receives a low level signal, the terminal DN receives a high level signal at the same time. Thus, the PMOS transistor P12 and the NMOS transistor N10 are turned on and the PMOS transistor P10 and the NMOS transistor N12 are turned off. Therefore, current flows through the resistor 14 from the terminal QN to the terminal Q, and the constant voltage difference between the terminals Q and QN is generated and the voltage level at the terminals Q and QN is controlled by the comparator 16.
The voltage level at the terminals Q and QN is controlled by the comparator 16 to reach demand values when the signals provided to the terminals DN and D are in low frequency.
However, the voltage difference between the terminals DN and D is low because the current is fixed when data is transmitted at high frequency.
The object of the present invention is thus to provide a driving circuit operating at high speed. In addition, the driving circuit provides output signal with fixed voltage difference and adjustable boundary.
To achieve the above-mentioned object, the present invention provides a driving circuit for outputting high-frequency signal. The first operational amplifier includes a first first input terminal coupled to a first reference voltage, a first second input terminal and a first output terminal. The second operational amplifier includes a second first input terminal coupled to a second reference voltage, a second second input terminal and a second output terminal. The first first-type MOS transistor includes a first drain coupled to a first voltage level, a first gate coupled to the first output terminal and a first source coupled to the first second input terminal. The first second-type MOS transistor includes a second drain coupled to a second voltage level, a second gate coupled to the second output terminal and a second source coupled to the second second input terminal. The matching resistor having a predetermined resistance is coupled between the first source and the second source. The second first-type MOS transistor includes a third drain coupled to the first voltage level, and a third gate coupled to the first output terminal and a third source. The second second-type MOS transistor includes a fourth drain coupled to the second voltage level, a fourth gate coupled to the second output terminal and a fourth source. The output resistor includes a first terminal, a second terminal and the predetermined resistance. The switching device connects the first terminal and the third source and the second terminal and the fourth source or connecting the first terminal and the fourth source and the second terminal and the third source.